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Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface
AD5415
FEATURES
On-chip 4-quadrant resistors allow flexible output ranges 10 MHz multiplying bandwidth 50 MHz serial interface 2.5 V to 5.5 V supply operation 10 V reference input Extended temperature range: -40C to +125C 24-lead TSSOP package Guaranteed monotonic Power-on reset Daisy-chain mode Readback function 0.5 A typical current consumption
GENERAL DESCRIPTION
The AD54151 is a CMOS 12-bit, dual-channel, current output digital-to-analog converter. This device operates from a 2.5 V to 5.5 V power supply, making it suited to battery-powered applications as well as many other applications. The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external current-to-voltage precision amplifier. In addition, this device contains all the 4-quadrant resistors necessary for bipolar operation and other configuration modes. This DAC utilizes a double-buffered 3-wire serial interface that is compatible with SPI(R), QSPITM, MICROWIRETM, and most DSP interface standards. In addition, a serial data out pin (SDO) allows for daisy-chaining when multiple packages are used. Data readback allows the user to read the contents of the DAC register via the SDO pin. On power-up, the internal shift register and latches are filled with zeros, and the DAC outputs are at zero scale. As a result of manufacture on a CMOS submicron process, this part offers excellent 4-quadrant multiplication characteristics, with large-signal multiplying bandwidths of 10 MHz.
1
APPLICATIONS
Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming
US Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
R3A R2_3A R3 2R R2 2R R2A VREFA R1A R1 2R RFB 2R RFBA INPUT REGISTER DAC REGISTER 12-BIT R-2R DAC A IOUT1A IOUT2A
VDD SYNC SCLK SDIN SDO LDAC
AD5415
SHIFT REGISTER
INPUT REGISTER CLR GND POWER-ON RESET
DAC REGISTER
12-BIT R-2R DAC B
IOUT1B IOUT2B RFBB
04461-0-001
R3 2R R3B R2_3B
R2 2R R2B
R1 2R VREFB R1B
RFB 2R
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD5415 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Terminology ...................................................................................... 9 Typical Performance Characteristics ........................................... 10 General Description ....................................................................... 15 DAC Section................................................................................ 15 Unipolar Mode............................................................................ 15 Bipolar Operation....................................................................... 16 Stability ........................................................................................ 16 Single-Supply Applications............................................................ 17 Voltage Switching Mode of Operation .................................... 17 Positive Output Voltage ............................................................. 17 Adding Gain................................................................................ 17 Divider or Programmable Gain Element ................................ 17 Reference Selection .................................................................... 18 Amplifier Selection .................................................................... 18 Serial Interface ................................................................................ 20 Low Power Serial Interface ....................................................... 20 Control Register ......................................................................... 20 SYNC Function........................................................................... 21 Daisy-Chain Mode ..................................................................... 21 Standalone Mode........................................................................ 21 LDAC Function .......................................................................... 21 Microprocessor Interfacing....................................................... 22 PCB Layout and Power Supply Decoupling................................ 24 Evaluation Board for the DAC ................................................. 24 Power Supplies for the Evaluation Board................................ 24 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28
REVISION HISTORY
7/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5415 SPECIFICATIONS
Temperature range for Y Version: -40C to +125C. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2A, IOUT2B = 0 V; all specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP1177, ac performance with AD8038, unless otherwise noted. Table 1.
Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temperature Coefficient1 Bipolar Zero Code Error Output Leakage Current REFERENCE INPUT1 Reference Input Range VREFA, VREFB Input Resistance VREFA to VREFB Input Resistance Mismatch R1, RFB Resistance R2, R3 Resistance R2 to R3 Resistance Mismatch DIGITAL INPUTS/OUTPUT1 Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth Output Voltage Settling Time Min Typ Max 12 1 -1/+2 25 5 25 1 10 10 10 1.6 20 20 0.06 Unit Bits LSB LSB mV ppm FSR/C mV nA nA V k % k k % V V V A pF V V V V MHz ns Conditions
Guaranteed monotonic
Data = 0x0000, TA = 25C, IOUT1 Data = 0x0000, IOUT1 Typical Resistor TC = -50 ppm/C DAC input resistance Typ = 25C, Max = 125C
8
12 2.5 24 24 0.18
16 16
Typ = 25C, Max = 125C VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
1.7 0.8 0.7 1 10 0.4 VDD - 1 0.4 VDD - 0.5 10 90
ISINK = 200 A ISOURCE = 200 A ISINK = 200 A ISOURCE = 200 A VREF = 5 V p-p, DAC loaded all 1s Measured to 4 mV of FS; RLOAD = 100 , CLOAD = 0s, 15 pF, DAC latch alternately loaded with 0s and 1s 1 LSB change around major carry, VREF = 0 V DAC latch loaded with all 0s, reference = 10 kHz DAC latches loaded with all 0s DAC latches loaded with all 1s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s VREF = 5 V p-p, all 1s loaded, f = 1 kHz VREF = 5 V, sine wave generated from digital code @ 1 kHz
160
Digital Delay Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density
20 3
40 -75 2 4
5 -75 -75 25
ns nV-s dB pF pF nV-s dB dB nV/Hz
Rev. 0 | Page 3 of 28
AD5415
Parameter SFDR Performance (Wideband) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT SFDR Performance (Narrow-Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50k Hz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50k Hz fOUT Intermodulation Distortion Clock = 10 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz Clock = 25 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz POWER REQUIREMENTS Power Supply Range IDD Power Supply Sensitivity1 Min Typ Max Unit Conditions
55 63 65 50 60 62
dB dB dB dB dB dB
73 80 87 70 75 80
dB dB dB dB dB dB
65 72 51 65 2.5 5.5 10 0.001
dB dB dB dB V A %/%
Logic inputs = 0 V or VDD VDD = 5%
1
Guaranteed by design and characterization, not subject to production test.
Rev. 0 | Page 4 of 28
AD5415
TIMING CHARACTERISTICS
Temperature range for Y Version: -40C to +125C. See Figure 2 and Figure 3. Guaranteed by design and characterization, not subject to production test. All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t122 Limit at TMIN, TMAX 50 20 8 8 13 5 4 5 30 0 12 10 25 60 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments1 Maximum clock frequency SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time Data setup time Data hold time SYNC rising edge to SCLK falling edge Minimum SYNC high time SCLK falling edge to LDAC falling edge LDAC pulse width SCLK falling edge to LDAC rising edge SCLK active edge to SDO valid, strong SDO driver SCLK active edge to SDO valid, weak SDO driver
1 2
Falling or rising edge as determined by the control bits of serial word. Strong or weak SDO driver selected via the control register. Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in Figure 4.
t1
SCLK
t8
SYNC
t4
t2
t3 t7
t6 t5
DIN DB15 DB0
t9
LDAC1
t10
t11
LDAC2
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 2. Standalone Mode Timing Diagram
Rev. 0 | Page 5 of 28
04461-0-002
NOTES 1ASYNCHRONOUS LDAC UPDATE MODE 2SYNCHRONOUS LDAC UPDATE MODE
AD5415
t1
SCLK
t4
SYNC
t2
t3
t7
t6 t5
SDIN DB15 (N) DB0 (N) DB15 (N+1) DB0 (N+1)
t8
t12
SDO DB15 (N) DB0 (N)
04461-0-003
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
200A
IOL
TO OUTPUT PIN
VOH (MIN) + VOL (MAX) CL 50pF 200A IOH 2
04461-0-004
Figure 4. Load Circuit for SDO Timing Specifications
Rev. 0 | Page 6 of 28
AD5415 ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up. TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND VREF, RFB to GND IOUT1, IOUT2 to GND Input Current to Any Pin except Supplies Logic Inputs and Output1 Operating Temperature Range Extended (Y Version) Storage Temperature Range Junction Temperature 24-Lead TSSOP JA Thermal Impedance Lead Temperature, Soldering (10 seconds) IR Reflow, Peak Temperature (<20 seconds) Rating -0.3 V to +7 V -12 V to +12 V -0.3 V to +7 V 10 mA -0.3 V to VDD + 0.3 V -40C to +125C -65C to +150C 150C 128C/W 300C 235C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Overvoltages at SCLK, SYNC, and DIN are clamped by internal diodes. Current should be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 7 of 28
AD5415 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOUT1A IOUT2A RFBA R1A R2A R2_3A R3A VREFA GND
1 2 3 4 5 6 24 IOUT1B 23 IOUT2B 22 RFBB 21 R1B
TOP VIEW 19 R2_3B 7 (Not to Scale) 18 R3B
8 9 17 VREFB 16 VDD 15 CLR 14 SYNC 13 SDO
04461-0-005
AD5415
20 R2B
LDAC 10 SCLK 11 SDIN 12
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4-7 8 9 10 Mnemonic IOUT1A IOUT2A RFBA R1A-R3A VREFA GND LDAC Function DAC A Current Output. DAC A Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to achieve single-supply operation. DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external amplifier output. DAC A 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with minimum external components. DAC A Reference Voltage Input Pin. Ground Pin. Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected whereby the DAC is updated on the 16th clock falling edge when the device is in standalone mode or on the rising edge of SYNC when in daisy-chain mode. Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of SCLK. Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to the rising edge. Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes the DAC register contents available for readback on the SDO pin, clocked out on the next 16 opposite clock edges to the active clock edge. Active Low Control Input. The frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on the active edge of the following clocks. In standalone mode, the serial interface counts clocks, and data is latched to the shift register on the 16th active clock edge. Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the user to enable the hardware CLR pin as a clear to zero scale or midscale, as required. Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. DAC B Reference Voltage Input Pin. DAC B 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with minimum of external components. DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external amplifier output. DAC B Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to achieve single-supply operation. DAC B Current Output.
11
SCLK
12
SDIN
13
SDO
14
SYNC
15 16 17 18-21 22 23 24
CLR VDD VREFB R1B-R3B RFBB IOUT2B IOUT1B
Rev. 0 | Page 8 of 28
AD5415 TERMINOLOGY
Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero scale and full scale, and is normally expressed in LSB or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference in the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF - 1 LSB. Gain error of the DACs is adjustable to zero with external resistance. Output Leakage Current Output leakage current is current that flows in the DAC ladder switches when they are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND. Output Current Settling Time The amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 resistor to ground. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s depending upon whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activity on the device's digital inputs is capacitively coupled through the device to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error The error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal when all 0s are loaded to the DAC. Digital Crosstalk The glitch impulse transferred to the outputs of one DAC in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of the other DAC. It is expressed in nV-s. Analog Crosstalk The glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa), while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. Channel-to-Channel Isolation The proportion of input signal from one DAC reference input that appears at the output of the other DAC and is expressed in dB. Harmonic Distortion The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the total harmonic distortion (THD). Usually only the lowerorder harmonics are included, such as second to fifth.
THD = 20 log
(V2 2 + V3 2 + V4 2 + V5 2 )
V1
Intermodulation Distortion The DAC is driven by two combined sine wave references of frequencies fa and fb. Distortion products are produced at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3 ... Intermodulation terms are those for which m or n is not equal to zero. The second-order terms include (fa + fb) and (fa - fb) and the third-order terms are (2fa + fb), (2fa - fb), (f + 2fa + 2fb) and (fa - 2fb). IMD is defined as
IMD = 20 log
(rms sum of the sum and diff distortion products )
rms amplitude of the fundamental
Compliance Voltage Range The maximum range of (output) terminal voltage for which the device provides the specified characteristics.
Rev. 0 | Page 9 of 28
AD5415 TYPICAL PERFORMANCE CHARACTERISTICS
1.0 0.8 0.6 0.4 TA = 25C VREF = 10V VDD = 5V -0.40 TA = 25C VREF = 10V VDD = 5V -0.45
-0.50
0 -0.2 -0.4 -0.6 -0.8
04461-0-006
DNL (LSB)
INL (LSB)
0.2
-0.55
-0.60 MIN DNL -0.65
0
500
1000
1500
2000 CODE
2500
3000
3500
4000
2
3
4
5
6
7
8
9
10
REFERENCE VOLTAGE
Figure 6. INL vs. Code (12-Bit DAC)
Figure 9. DNL vs. Reference Voltage
1.0 0.8 0.6 0.4
ERROR (mV) DNL (LSB)
5
TA = 25C VREF = 10V VDD = 5V
4 3 2 1 0 -1 -2 -3 -4
04461-0-007
VDD = 5V
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
VDD = 2.5V
VREF = 10V
04461-0-010
04461-0-011
-5 -60
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (C)
Figure 7. DNL vs. Code (12-Bit DAC)
Figure 10. Gain Error vs. Temperature
0.6 0.5 0.4 MAX INL
CURRENT (mA)
8 TA = 25C 7 6 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) VDD = 3V VDD = 2.5V VDD = 5V
0.3
INL (LSB)
0.2 0.1 0 MIN INL -0.1 -0.2
04461-0-008
TA = 25C VREF = 10V VDD = 5V
-0.3 2 3 4 5 6 7 8 9 10 REFERENCE VOLTAGE
Figure 8. INL vs. Reference Voltage
Figure 11. Supply Current vs. Logic Input Voltage
Rev. 0 | Page 10 of 28
04461-0-009
-1.0
-0.70
AD5415
1.6 1.4 1.2 IOUT1 VDD 5V
IOUT LEAKAGE (nA)
1.0 0.8 IOUT1 VDD 3V 0.6 0.4 0.2
04461-0-012
0 -40
-20
0
20
40
60
80
100
120
1
10
100
TEMPERATURE (C)
1k 10k 100k FREQUENCY (Hz)
1M
10M
100M
Figure 12. Iout1 Leakage Current vs. Temperature
Figure 15. Reference Multiplying Bandwidth vs. Frequency and Code
0.50 0.45 VDD = 5V 0.40 0.35 TA = 25C
0.2
0
CURRENT (A)
ALL 0s 0.25 0.20 0.15 0.10 0.05
04461-0-013
ALL 1s VDD = 2.5V
GAIN (dB)
0.30
-0.2
-0.4
ALL 1s
ALL 0s
-0.6
TA = 25C VDD = 5V VREF = 3.5V CCOMP = 1.8pF AD8038 AMPLIFIER 1 10 100 1k 10k 100k 1M 10M 100M
04461-0-016
0 -60
-0.8 FREQUENCY (Hz)
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (C)
Figure 13. Supply Current vs. Temperature
Figure 16. Reference Multiplying Bandwidth-All Ones Loaded
14 TA = 25C LOADING ZS TO FS VDD = 5V
3
TA = 25C VDD = 5V
12
0
10
IDD (mA)
8
GAIN (dB)
-3
6
VDD = 3V
4 VDD = 2.5V 2
-6
VREF = 2V, AD8038 CC 1.47pF VREF = 2V, AD8038 CC 1pF VREF = 0.15V, AD8038 CC 1pF VREF = 0.15V, AD8038 CC 1.47pF VREF = 3.51V, AD8038 CC 1.8pF 100k 1M FREQUENCY (Hz) 10M 100M
04461-0-017
1
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
04461-0-014
0
-9 10k
Figure 14. Supply Current vs. Update Rate
Figure 17. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor
Rev. 0 | Page 11 of 28
04461-0-015
6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -96 -102
TA = 25C LOADING ZS TO FS
ALL ON DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
GAIN (dB)
ALL OFF
TA = 25C VDD = 5V VREF = 3.5V INPUT CCOMP = 1.8pF AD8038 AMPLIFIER
AD5415
0.045 0.040 0.035
OUTPUT VOLTAGE (V)
-60
7FF TO 800H VDD = 5V TA = 25C VREF = 0V AD8038 AMPLIFIER CCOMP = 1.8pF
-65
TA = 25C VDD = 3V VREF = 3.5V p-p
0.030 VDD = 3V
THD + N (dB)
0.025 0.020 0.015
-70
-75
800 TO 7FFH 0.010 0.005 0 -0.005 0 20 40 60 80 100 120 140 160 180 200
04461-0-018
VDD = 3V
-80
-85
VDD = 5V
1
10
100
1k
10k
100k
1M
TIME (ns)
FREQUENCY (Hz)
Figure 18. Midscale Transition, VREF = 0 V
Figure 21. THD and Noise vs. Frequency
-1.68 7FF TO 800H -1.69 VDD = 5V -1.70
OUTPUT VOLTAGE (V)
100
TA = 25C VREF = 3.5V AD8038 AMPLIFIER CCOMP = 1.8pF
MCLK = 1MHz 80
-1.71 -1.72 -1.73 -1.74 -1.75 -1.76 800 TO 7FFH
04461-0-019
SFDR (dB)
60
MCLK = 200kHz MCLK = 0.5MHz
VDD = 3V VDD = 5V VDD = 3V
40
20 TA = 25C VREF = 3.5V AD8038 AMPLIFIER
0
20
40
60
80
100
120
140
160
180
200
0
20
40
60
80
100
120
140
160
180
200
TIME (ns)
fOUT (kHz)
Figure 19. Midscale Transition, VREF = 3.5 V
Figure 22. Wideband SFDR vs. fOUT Frequency
20 0 -20
TA = 25C VDD = 3V AMP = AD8038
90 80 MCLK = 5MHz 70 60 MCLK = 10MHz
PSRR (dB)
SFDR (dB)
-40
FULL SCALE
-60 -80 -100
50 40 30 20 10 TA = 25C VREF = 3.5V AD8038 AMPLIFIER 0 100 200 300 400 500 600 700 800 900 1000
04461-0-023
MCLK = 25MHz
ZERO SCALE
-120
04461-0-020
1
10
100
1k
10k
100k
1M
10M
0
FREQUENCY (Hz)
fOUT (kHz)
Figure 20. Power Supply Rejection vs. Frequency
Figure 23. Wideband SFDR vs. fOUT Frequency
Rev. 0 | Page 12 of 28
04461-0-022
-1.77
0
04461-0-021
-0.010
-90
AD5415
0 -10 -20 -30
SFDR (dB) SFDR (dB)
TA = 25C VDD = 5V AMP = AD8038 65k CODES
0 -10 -20 -30 -40
TA 25C = VDD = 3V AMP = AD8038 65k CODES
-40 -50 -60 -70 -80
04461-0-024
-50 -60 -70 -80 -90
-90
0 2 4 6 8 FREQUENCY (MHz) 10 12
-100 250
300
350
400
450 500 550 600 FREQUENCY (MHz)
650
700
750
Figure 24. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
Figure 27. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
0 -10 -20 -30
SFDR (dB)
TA 25C = VDD = 5V AMP = AD8038 65k CODES
20 0 -20
SFDR (dB)
TA 25C = VDD = 3V AMP = AD8038 65k CODES
-40 -50 -60 -70 -80 -90
04461-0-025
-40 -60 -80
-100 -120 50
04461-0-028 04461-0-029
-100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (MHz) 4.0 4.5 5.0
60
70
80
90 100 110 120 FREQUENCY (MHz)
130
140
150
Figure 25. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
Figure 28. Narrow-Band SFDR, fOUT = 100 kHz, MCLK = 25 MHz
0
-10
-20
TA = 25C VDD = 5V AMP = AD8038 65k CODES
0 -10 -20 -30 -40
(dB)
TA 25C = VDD = 3V AMP = AD8038 65k CODES
-30
SFDR (dB)
-40
-50 -60
-50
-60
-70 -80 -90
04461-0-026
-70
-80
-90
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (MHz) 4.0 4.5 5.0
-100 70 75 80 85 90 100 105 95 FREQUENCY (MHz) 110 115 120
Figure 26. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
Figure 29. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
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04461-0-027
AD5415
0 -10 -20 -30 -40
(dB)
TA 25C = VDD = 5V AMP = AD8038 65k CODES
OUTPUT NOISE (nV/ Hz)
300 ZERO SCALE LOADED TO DAC 250 MIDSCALE LOADED TO DAC FULL SCALE LOADED TO DAC 200
TA = 25C AMP = AD8038
-50 -60 -70 -80 -90
150
100
50
04461-0-031
-100 0 50 100 150 200 250 FREQUENCY (kHz) 300 350 400
04461-0-030
0 100
1k
10k FREQUENCY (Hz)
100k
Figure 30. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
Figure 31. Output Noise Spectral Density
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AD5415 GENERAL DESCRIPTION
DAC SECTION
The AD5415 is a 12-bit, dual-channel, current output DAC consisting of standard inverting R to 2R ladder configuration. A simplified diagram of one DAC channel for the AD5415 is shown in Figure 32. The feedback resistor RFB has a value of 2R. The value of R is typically 10 k (minimum 8 k and maximum 12 k). If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of the digital input code. Therefore, the input resistance presented at VREF is always constant.
R VREFA 2R S1 2R S2 2R S3 2R S12 2R 2R RFBA IOUT1A IOUT2A DAC DATA LATCHES AND DRIVERS
04461-0-032
VOUT = -VREF x D/2n where: D is the fractional representation of the digital word loaded to the DAC, in the range of 0 to 4095. n is the number of bits. Note that the output voltage polarity is opposite the VREF polarity for dc reference voltages. These DACs are designed to operate with either negative or positive reference voltages. The VDD power pin is used only by the internal digital logic to drive the DAC switches' on and off states. These DACs are also designed to accommodate ac reference input signals in the range of -10 V to +10 V. With a fixed 10 V reference, the circuit in Figure 32 gives a unipolar 0 V to -10 V output voltage swing. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. Table 5 shows the relationship between digital code and expected output voltage for unipolar operation.
Table 5. Unipolar Code Table
Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 Analog Output (V) -VREF (4095/4096) -VREF (2048/4096) = -VREF/2 -VREF (1/4096) -VREF (0/4096) = 0
R
R
Figure 32. Simplified Ladder
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output, bipolar output, or in single-supply modes of operation in unipolar mode or 4-quadrant multiplication in bipolar mode.
UNIPOLAR MODE
Using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 33. When an output amplifier is connected in unipolar mode, the output voltage is given by
VDD R1A R1 2R R2A R2 2R R2_3A R3 2R RFB 2R
RFBA C1
AD5415
12-BIT DAC A R
IOUT1A A1 IOUT2A VOUT = 0V TO -VIN
R3A
AGND AGND VREFA SYNC SCLK SDIN GND
uCONTROLLER
AGND
NOTES: 1DAC B OMITTED FOR CLARITY. 2C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 33. Unipolar Operation
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04461-0-033
AD5415
BIPOLAR OPERATION
In some applications, it might be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and the on chip 4-quadrant resistors, as shown in Figure 34. When in bipolar mode, the output voltage is given by VOUT = VREF x D/2n - 1 -VREF where D is the fractional representation of the digital word loaded to the DAC, in the range of 0 to 4095. n is the number of bits. When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation.
Table 6. Bipolar Code Table
Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 Analog Output (V) +VREF (2047/2048) 0 -VREF (2047/2048) VREF (2048/2048)
STABILITY
In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as close as possible, and proper PCB layout techniques must be employed. Because every code change corresponds to a step function, gain peaking can occur if the op amp has limited GBP and there is excessive parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into the open loop response that can cause ringing or instability in the closed loop application's circuit. An optional compensation capacitor, C1, can be added in parallel with RFB for stability, as shown in Figure 33 and Figure 34. Too small a value of C1 can produce ringing at the output, while too large a value can adversely affect the settling time. C1 should be found empirically, but 1 pF to 2 pF is generally adequate for the compensation.
VDD
R1A R1 2R RFB 2R RFBA C1
VIN
R2A R2 2R R2_3A R3 2R
AD5415
12-BIT DAC A R
IOUT1A A1 IOUT2A VOUT = -VIN TO +VIN
A1
R3A
AGND VREFA SYNC SCLK SDIN GND
AGND uCONTROLLER AGND
NOTES: 1DAC B OMITTED FOR CLARITY. 2C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 34. Bipolar Operation
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04461-0-034
AD5415 SINGLE-SUPPLY APPLICATIONS
VOLTAGE SWITCHING MODE OF OPERATION
Figure 35 shows these DACs operating in the voltage switching mode. The reference voltage, VIN, is applied to the IOUT1 pin, IOUT2 is connected to AGND, and the output voltage is available at the VREF terminal. In this configuration, a positive reference voltage results in a positive output voltage, making singlesupply operation possible. The output from the DAC is voltage at a constant impedance (the DAC ladder resistance). Therefore, an op amp is necessary to buffer the output voltage. The reference input no longer sees a constant input impedance, but one that varies with code. So, the voltage input should be driven from a low impedance source.
VDD R1 R2
+5V -2.5V 1/2 AD8552 GND -5V VDD = 5V ADR03 VOUT VIN GND VDD VREF RFB IOUT1 12-BIT DAC IOUT2 VOUT = 0 TO +2.5V 1/2 AD8552 C1
NOTES: 1ADDITIONAL PINS OMITTED FOR CLARITY. 2C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 36. Positive Voltage Output with Minimum of Components
ADDING GAIN
In applications where the output voltage is required to be greater than VIN, gain can be added with an additional external amplifier, or it can also be achieved in a single stage. It is important to take into consideration the effect of temperature coefficients of the thin film resistors of the DAC. Simply placing a resistor in series with the RFB resistor causes mismatches in the temperature coefficients, resulting in larger gain temperature coefficient errors. Instead, the circuit in Figure 37 is a recommended method of increasing the gain of the circuit. R1, R2, and R3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains of greater than 1 are required.
VDD
VIN
RFB IOUT1 IOUT2
VDD VREF GND VOUT
Figure 35. Single-Supply Voltage Switching Mode
Note that VIN is limited to low voltages, because the switches in the DAC ladder no longer have the same source-drain drive voltage. As a result, their on resistance differs and this degrades the integral linearity of the DAC. Also, VIN must not go negative by more than 0.3 V or an internal diode is turned on, exceeding the maximum ratings of the device. In this type of application, the full range of multiplying capability of the DAC is lost.
04461-0-035
NOTES 1. SIMILAR CONFIGURATION FOR DACB 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
VDD VIN R2 VREF
RFB IOUT1
C1
12-BIT DAC IOUT2 GND R2 R3
VOUT
POSITIVE OUTPUT VOLTAGE
The output voltage polarity is opposite to the VREF polarity for dc reference voltages. To achieve a positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistors' tolerance errors. To generate a negative reference, the reference can be level-shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and -2.5 V, respectively, as shown in Figure 36.
GAIN =
R2 + R3 R2
04461-0-037
R2R3 R1 = R2 + R3 NOTES: 1ADDITIONAL PINS OMITTED FOR CLARITY. 2C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 37. Increasing the Gain of the Current Output DAC
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves to many different applications. If this type of DAC is connected as the feedback element of an op amp and RFB is used as the input resistor, as shown in Figure 38, then the output voltage is inversely proportional to the digital input fraction, D. For D equal to 1 - 2n, the output voltage is VOUT = -VIN/D = -VIN/(1 -2-n)
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04461-0-036
AD5415
VDD
VIN
RFB IOUT1 IOUT2 GND VREF VDD
VOUT
04461-0-038
overall specification to within 1 LSB over the temperature range 0C to 50C dictates that the maximum system drift with temperature should be less than 78 ppm/C. A 12-bit system with the same temperature range to overall specification within 2 LSB requires a maximum drift of 10 ppm/C. By choosing a precision reference with a low output temperature coefficient, this error source can be minimized. Table 7 suggests some of the references available from Analog Devices that are suitable for use with this range of current output DACs.
NOTE: 1ADDITIONAL PINS OMITTED FOR CLARITY.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. The input offset voltage of an op amp is multiplied by the variable gain (due to the code-dependent output resistance of the DAC) of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier's input offset voltage. This output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, could cause the DAC to be nonmonotonic. The input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, RFB. Most op amps have input bias currents low enough to prevent any significant errors in 12-bit applications. Common-mode rejection of the op amp is important in voltage switching circuits, because it produces a code-dependent error at the voltage output of the circuit. Most op amps have adequate common-mode rejection for use at 12-bit resolution. Provided that the DAC switches are driven from true wideband low impedance sources (VIN and AGND), they settle quickly. Consequently, the slew rate and settling time of a voltage switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it is important to minimize capacitance at the VREF node (voltage output node in this application) of the DAC. This is done by using low inputs, capacitance buffer amplifiers, and careful board design. Most single-supply circuits include ground as part of the analog signal range, which in turn requires an amplifier that can handle rail-to-rail signals. A large range of single-supply amplifiers is available from Analog Devices.
Figure 38. Current-Steering DAC Used as a Divider or Programmable Gain Element
As D is reduced, the output voltage increases. For small values of the digital fraction, D, it is important to ensure that the amplifier does not saturate and also that the required accuracy is met. For example, an 8-bit DAC driven with the binary code 0x10 (0001 0000), that is, 16 decimal, in the circuit of Figure 37 should cause the output voltage to be 16 times VIN. However, if the DAC has a linearity specification of 0.5 LSB, then D can, in fact, have a weight anywhere in the range 15.5/256 to 16.5/256, so that the possible output voltage is in the range 15.5 VIN to 16.5 VIN, an error of 3% even though the DAC itself has a maximum error of 0.2%. DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the DAC. Because only a fraction D of the current into the VREF terminal is routed to the IOUT1 terminal, the output voltage has to change as follows:
Output Error Voltage Due to DAC Leakage = (Leakage x R)/D
where R is the DAC resistance at the VREF terminal. For a DAC leakage current of 10 nA, R = 10 k, and a gain (that is, 1/D) of 16, the error voltage is 1.6 mV.
REFERENCE SELECTION
When selecting a reference for use with the AD54xx series of current output DACs, pay attention to the reference's output voltage temperature coefficient specification. This parameter affects not only the full-scale error, but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its
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AD5415
Table 7. ADI Precision References for Use with AD54xx DACs
Reference ADR01 ADR02 ADR03 ADR425 Output Voltage (V) 10 5 2.5 5 Initial Tolerance (%) 0.1 0.1 0.2 0.04 Temp. Drift (ppm/C) 3 3 3 3 0.1 Hz to 10 Hz Noise 20 V p-p 10 V p-p 10 V p-p 3.4 V p-p Package SC70, TSOT, SOIC SC70, TSOT, SOIC SC70, TSOT, SOIC MSOP, SOIC
Table 8. Precision ADI Op Amps for Use with AD54xx DACs
Part No. OP97 OP1177 AD8551 Max Supply Voltage (V) 20 18 6 VOS (max) V 25 60 5 IB (max) nA 0.1 2 0.05 GBP MHz 0.9 1.3 1.5 Slew Rate (V/s) 0.2 0.7 0.4
Table 9. High Speed ADI Op Amps for Use with AD54xx DACs
Part No. AD8065 AD8021 AD8038 Max Supply Voltage (V) 12 12 5 VOS (max) V 1500 1000 3000 IB (max) nA 0.01 1000 0.75 BW @ ACL MHz 145 200 350 Slew Rate (V/s) 180 100 425
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AD5415 SERIAL INTERFACE
The AD5415 has an easy-to-use 3-wire interface, which is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. Data is written to the device in 16-bit words. Each 16-bit word consists of four control bits and 12 data bits, as shown in Figure 39.
SDO Control (SDO1 and SDO2)
The SDO bits enable the user to control the SDO output driver strength, disable the SDO output, or configure it as an opendrain driver. The strength of the SDO driver affects the timing of t12 and, when stronger, allows a faster clock cycle to be used.
Table 10. SDO Control Bits
SDO2 0 0 1 1 SDO1 0 1 0 1 Function Full SDO Driver SDO Configured as Open Drain Weak SDO Driver Disable SDO Output
LOW POWER SERIAL INTERFACE
To minimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. The SCLK and DIN input buffers are powered down on the rising edge of SYNC.
DAC Control Bits C3 to C0
Control bits C3 to C0 allow control of various functions of the DAC, as shown in Table 11. Default settings of the DAC at power-on are as follows. Data is clocked into the shift register on falling clock edges; daisy-chain mode is enabled. The device powers on with zero-scale load to the DAC register and IOUT lines. The DAC control bits allow the user to adjust certain features at power-on. For example, daisy-chaining can be disabled when not in use, active clock edge can be changed to rising edge, and DAC output can be cleared to either zero scale or midscale. The user can also initiate a readback of the DAC register contents for verification purposes.
Daisy-Chain Control (DSY)
DSY enables or disables daisy-chain mode. A 1 enables daisychain mode; a 0 disables it. When disabled, a readback request is accepted, SDO is automatically enabled, the DAC register contents of the relevant DAC are clocked out on SDO, and, when complete, SDO is disabled again.
Hardware CLR Bit (HCLR)
The default setting for the hardware CLR pin is to clear the registers and DAC output to zero code. A 1 in the HCLR bit clears the DAC outputs to midscale; a 0 clears them to zero scale.
CONTROL REGISTER
(Control Bits = 1101)
While maintaining software compatibility with the singlechannel current output DACs (AD5426/AD5433/AD5443), this DAC also features some additional interface functionality. Simply set the control bits to 1101 to enter control register mode. Figure 40 shows the contents of the control register, the functions of which are described in the following sections.
Active Clock Edge (SCLK)
The default active clock edge is the falling edge. Write a 1 to this bit to clock data in on the rising edge; write a 0 to clock it on the falling edge.
DB15 (MSB) C3 C2 C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB0 (LSB)
04461-0-039 04461-0-040
DB1
DB0
CONTROL BITS
DATA BITS
Figure 39. AD5415 12-Bit Input Shift Register Contents
DB15 (MSB) 1 1 0 1 SDO1 SDO2 DSY HCLR SCLK X X X X X
DB0 (LSB) X X
CONTROL BITS
Figure 40. Control Register Loading Sequence
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AD5415
Table 11. DAC Control Bits
C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC A and B A A A B B B A and B A and B - - - - - - - Function No Operation (Power-On Default) Load and Update Initiate Readback Load Input Register Load and Update Initiate Readback Load Input Register Update DAC Outputs Load Input Registers Daisy-Chain Disable Clock Data to Shift Register on Rising Edge Clear DAC Output to Zero Clear DAC Output to Midscale Control Word Reserved No Operation
SYNC FUNCTION
SYNC is an edge-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC falling to SCLK falling edge setup time, t4.
When control bits are 0000, the device is in no-operation mode. This might be useful in daisy-chain applications, where the user does not want to change the settings of a particular DAC in the chain. Simply write 0000 to the control bits for that DAC, and the following data bits are ignored.
STANDALONE MODE
After power-on, writing 1001 to the control word disables daisychain mode. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure that the correct number of bits is shifted in and out of the serial shift registers. A SYNC edge during the 16-bit write cycle causes the device to abort the current write cycle. After the falling edge of the 16th SCLK pulse, data is automatically transferred from the input shift register to the DAC. In order for another serial transfer to take place, the counter must be reset by the falling edge of SYNC.
DAISY-CHAIN MODE
Daisy-chain mode is the default mode at power-on. To disable the daisy-chain function, write 1001 to the control word. In daisy-chain mode, the internal gating on SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid for the next device on the falling edge (default). By connecting this line to the DIN input on the next device in the chain, a multidevice interface is constructed. Sixteen clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 16N, where N is the total number of devices in the chain. (See the timing diagram in Figure 4.) When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data from being clocked into the input shift register. A burst clock containing the exact number of clock cycles can be used and SYNC taken high some time later. After the rising edge of SYNC, data is automatically transferred from each device's input shift register to the addressed DAC.
LDAC FUNCTION
The LDAC function allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected, whereby the DAC is updated on the 16th clock falling edge when the device is in standalone mode or on the rising edge of SYNC when in daisy-chain mode.
Software LDAC Function
Load and update mode also functions as a software update function, irrespective of the voltage level on the LDAC pin.
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AD5415
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5415 DAC is through a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5415 requires a 16-bit word, with the default being data valid on the falling edge of SCLK, but this is changeable using the control bits in the data-word.
Table 12. SPORT Control Register Setup
Name TFSW INVTFS DTYPE ISCLK TFSR ITFS SLEN Setting 1 1 00 1 1 1 1111 Description Alternate framing Active low frame signal Right-justify data Internal serial clock Frame every word Internal framing signal 16-bit data-word
ADSP-21xx to AD5415 Interface
The ADSP-21xx family of DSPs is easily interfaced to the AD5415 DAC without the need for extra glue logic. Figure 40 is an example of an SPI interface between the DAC and the ADSP-2191M. SCK of the DSP drives the serial data line, DIN. SYNC is driven from one of the port lines, in this case SPIxSEL.
ADSP-2191*
SPIxSEL MOSI SCK
80C51/80L51 to AD5415 Interface
A serial interface between the DAC and the 80C51 is shown in Figure 43. TXD of the 80C51 drives SCLK of the DAC serial interface, while RXD drives the serial data line, DIN. P3.3 is a bit-programmable pin on the serial port and is used to drive SYNC. When data is to be transmitted to the switch, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data correctly to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. Data on RXD is clocked out of the microcontroller on the rising edge of TXD and is valid on the falling edge. As a result, no glue logic is required between the DAC and microcontroller interface. P3.3 is taken high following the completion of this cycle. The 80C51 provides the LSB of its SBUF register as the first bit in the data stream. The DAC input register requires its data with the MSB as the first bit received. The transmit routine should take this into account.
8051*
TxD RxD
SCLK
SDIN SYNC
04461-0-043
AD5415*
SYNC SDIN SCLK
04461-0-041
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. ADSP-2191 SPI to AD5415 Interface
A serial interface between the DAC and DSP SPORT is shown in Figure 42. In this interface example, SPORT0 is used to transfer data to the DAC shift register. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. In a write sequence, data is clocked out on each rising edge of the DSP's serial clock and clocked into the DAC input shift register on the falling edge of its SCLK. The update of the DAC output takes place on the rising edge of the SYNC signal.
ADSP-2101/ ADSP-2103/ ADSP-2191*
AD5415*
AD5415*
TFS DT SYNC SDIN
P1.1
*ADDITIONAL PINS OMITTED FOR CLARITY
SCLK
SCLK
04461-0-042
Figure 43. 80C51/80L51 to AD5415 Interface
MC68HC11 Interface to AD5415 Interface
Figure 44 is an example of a serial interface between the DAC and the MC68HC11 microcontroller. The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR) = 1, Clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR); see the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the DAC interface, the MOSI output drives the serial data line (DIN) of the AD5516. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5516, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 42. ADSP-2101/ADSP-2103/ADSP-2191 SPORT to AD5415 Interface
Communication between two devices at a given clock speed is possible when the following specifications are compatible: frame sync delay and frame sync setup-and-hold, data delay and data setup-and-hold, and SCLK width. The DAC interface expects a t4 (SYNC falling edge to SCLK falling edge setup time) of 13 ns minimum. See the ADSP-21xx User Manual for information on clock and frame sync frequencies for the SPORT register. Table 12 shows the set up for the SPORT control register.
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AD5415
the transmit cycle. Data is transmitted MSB first. To load data to the DAC, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure.
MC68HC11*
PC7 SCK MOSI SYNC SCLK SDIN
04461-0-044
MICROWIRE*
SK SO CS
AD5415*
SCLK SDIN SYNC
04461-0-045
AD5415*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 45. MICROWIRE to AD5415 Interface
PIC16C6x/7x to AD5415 Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit (CKP) = 0. This is done by writing to the synchronous serial port control register (SSPCON); see the PIC16/17 Microcontroller User Manual. In this example, I/O port RA1 is used to provide a SYNC signal and enable the serial port of the DAC. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive write operations are required. Figure 46 shows the connection diagram.
PIC16C6x/7x*
SCK/RC3 SDI/RC4 RA1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 44. 68HC11/68L11 to AD5415 Interface
If the user wants to verify the data previously written to the input shift register, the SDO line can be connected to MISO of the MC68HC11, and, with SYNC low, the shift register clocks data out on the rising edges of SCLK.
MICROWIRE to AD5415 Interface
Figure 45 shows an interface between the DAC and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock, SK, and is clocked into the DAC input shift register on the rising edge of SK, which corresponds to the falling edge of the DAC's SCLK.
AD5415*
SCLK SDIN SYNC
04461-0-046
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 46. PIC16C6x/7x to AD5415 Interface
Rev. 0 | Page 23 of 28
AD5415 PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5415 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The DAC should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply located as close to the package as possible, ideally right up against the device. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the soldered side. It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize on high frequency performance, the I-to-V amplifier should be located as close to the device as possible.
EVALUATION BOARD FOR THE DAC
The evaluation board consists of an AD5415 DAC and a current-to-voltage amplifier, AD8065. Included on the evaluation board is a 10 V reference, ADR01. An external reference can also be applied via an SMB input. The evaluation kit consists of a CD-ROM with self-installing PC software to control the DAC. The software allows the user to write a code to the device.
POWER SUPPLIES FOR THE EVALUATION BOARD
The board requires 12 V and +5 V supplies. The +12 V VDD and VSS are used to power the output amplifier, while the +5 V is used to power the DAC (VDD1) and transceivers (VCC). Both supplies are decoupled to their respective ground plane with 10 F tantalum and 0.1 F ceramic capacitors.
Rev. 0 | Page 24 of 28
RFBA VDD1 R1A 16 VDD IOUT1A 6 J1 A IOUT2A R2A 9 GND R2-3A R3A A 7 VREF J8 LK2 21 20 J10 22 24 23 19 18 17 VSS 4 6 AD8065AR VDD VDD C25 10F +
V- V+
3 4 TP1 4
V- V+
C8 1.8pF VSS 2 3 VOUT
C7 10F + C8 0.1F
1 2 5 6 VDD C9 10F + C10 0.1F 7
+ C2 10F C1 0.1F
U3
VDD1
VDD1
VDD1
VDD
U1 AD5415
VREFA VREFA LK3 VIN B 8 R1B SCLK 11 SCLK R2B RFBB IOUT1B IOUT2B R2-3B R3B VREFB SDIN SYNC LDAC SDO CLR 12 14 10 13 15 J7 J6 J5 J4 J3 SDIN SYNC LDAC
4
C4 0.1F
R3 10k
R2 10k
R1 10k
VOUT
+VIN
3 U2 ADR01AR 1
GND TRIM
P1-3
SCLK
5 4
C4 0.1F
C3 10F
P1-2
SDIN
P1-4 LK1 AB CLR SDO
SYNC
P1-5
LDAC
Figure 47. Schematic of the AD5415 Evaluation Board
Rev. 0 | Page 25 of 28
2 3 7
P1-13
SDO
C18 C17 1.8pF C22 10F + C23 0.1F VSS 2 3 4
V- V+
P1-6
CLR
10F + C19 0.1F TP2 VOUT 6 7 J2 B
U4 U5
C24 0.1F VDD
C20 10F + C21 0.1F
P2-3 C11 0.1F C13 0.1F AGND VSS VDD1 + C14 10F + C12 10F
P2-2
P2-1
P2-4 C15 0.1F + C16 10F
P1-19 P1-20 P1-21 P1-22 P1-23 P1-24 P1-25 P1-26 P1-27 P1-28 P1-29 P1-30
04461-0-047
AD5415
AD5415
Figure 48. Component-Side Artwork
Figure 49. Silkscreen--Component-Side View (Top)
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04461-0-049
04461-0-048
AD5415
Figure 50. Solder-Side Artwork
Table 13. Overview of AD54xx Devices
Part No. AD5424 AD5426 AD5428 AD5429 AD5450 AD5432 AD5433 AD5439 AD5440 AD5451 AD5443 AD5444 AD5415 AD5445 AD5447 AD5449 AD5452 AD5446 AD5453 AD5553 AD5556 AD5555 AD5557 AD5543 AD5546 AD5545 AD5547 Resolution 8 8 8 8 8 10 10 10 10 10 12 12 12 12 12 12 12 14 14 14 14 14 14 16 16 16 16 No. DACs 1 1 2 2 1 1 1 2 2 1 1 1 2 2 2 2 1 1 1 1 1 2 2 1 1 2 2 INL(LSB) 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 0.5 0.25 1 0.5 1 1 1 1 0.5 1 2 1 1 1 1 2 2 2 2 Interface Parallel Serial Parallel Serial Serial Serial Parallel Serial Parallel Serial Serial Serial Serial Parallel Parallel Serial Serial Serial Serial Serial Parallel Serial Parallel Serial Parallel Serial Parallel Package RU-16, CP-20 RM-10 RU-20 RU-10 RJ-8 RM-10 RU-20, CP-20 RU-16 RU-24 RJ-8 RM-10 RM-8 RU-24 RU-20, CP-20 RU-24 RU-16 RJ-8, RM-8 RM-8 UJ-8, RM-8 RM-8 RU-28 RM-8 RU-38 RM-8 RU-28 RU-16 RU-38 Features 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 50 MHz Serial 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 50 MHz Serial 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 58 MHz Serial 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 4 MHz BW, 50 MHz Serial Clock 4 MHz BW, 20 ns WR Pulse Width 4 MHz BW, 50 MHz Serial Clock 4 MHz BW, 20 ns WR Pulse Width 4 MHz BW, 50 MHz Serial Clock 4 MHz BW, 20 ns WR Pulse Width 4 MHz BW, 50 MHz Serial Clock 4 MHz BW, 20 ns WR Pulse Width
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04461-0-050
AD5415 OUTLINE DIMENSIONS
7.90 7.80 7.70
24
13
4.50 4.40 4.30 6.40 BSC
1 12
PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153AD 1.20 MAX
SEATING PLANE
0.20 0.09
8 0
0.75 0.60 0.45
Figure 51. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5415YRU AD5415YRU-REEL AD5415YRU-REEL7 EVAL-AD5415EB Resolution 12 12 12 INL (LSBs) 1 1 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C Package Description TSSOP TSSOP TSSOP Evaluation Kit Package Option RU-24 RU-24 RU-24
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04461-0-7/04(0)
Rev. 0 | Page 28 of 28

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